As technology advances, semiconductor logic and memory devices require higher operation speed and accuracy to accommodate increasing performance demands. In particular, semiconductor logic devices such as CMOS (complementary metal oxide silicon) devices require low gate and contact resistivity to achieve high speed operation. In order to lower resistivity, polycide gate structures including a stacked arrangement of doped polysilicon and a silicide such as cobalt silicide (CoSi.sub.2) or titanium silicide (TiSi.sub.2) have been used.
To lower resistivity still further, it is desirable to use metal-strapped polysilicon gate structures which include a stacked arrangement of doped polysilicon and a metal. FIG. 16 shows a MOS transistor 1300 having such a metal-strapped polysilicon gate structure. Transistor 1300 is formed on a silicon substrate 1301 and is isolated from other elements formed on the substrate by shallow trench isolation region 1306. Spaced apart source/drain regions 1307 are formed in substrate 1301 and include lightly doped portions 1307a. The metal-strapped polysilicon gate structure includes a stacked arrangement of a doped (e.g., N+) polysilicon gate electrode 1302 and metal strap layer 1304. Metal strap layer 1304 may be formed of tungsten (W), for example. Polysilicon gate electrode 1302 is insulatively spaced from a channel region between source/drain regions 1307 by a gate dielectric film 1310. Silicide layers 1311 of titanium silicide (TiSi.sub.2), for example, formed on source/drain regions 1307 serve to reduce the resistivity of contacts to the source/drain layers. Sidewall insulating layer 1303 is formed on the sidewalls of the gate structure and an interlayer insulating layer 1309 of silicon dioxide (SiO.sub.2), for example, is formed on the transistor 1300. Openings 1305 in interlayer insulating layer 1309 expose silicide layers 1311 and metal wiring layers 1308 of, for example, Al--Cu fill in openings 1305.
While such metal-strapped polysilicon gate structures afford the advantage of low resistivity, a problem arises in that the process steps for forming the transistor must not result in undesirable reactions between the metal strap layer and the polysilicon gate electrode. Since such reactions can occur, for example, during heating steps greater than about 600.degree. C., it becomes difficult to integrate certain high temperature processes (such as a high temperature annealing for repairing substrate damage which occurs during the reactive ion etching of the gate structure or a high temperature annealing for activating source/drain implantations) into the manufacturing process of a transistor including a metal-strapped polysilicon gate structure. It is proposed in Y. Akasaka et al., "Low-Resistivity Poly-Metal Gate Electrode Durable for High-Temperature Processing." IEEE Transactions on Electron Devices, Vol. 43, No. 11, November 1996, pp. 1864-1869, which is incorporated herein in its entirety, that a thin layer of WN.sub.x, for example, be provided as a barrier layer between the doped polysilicon gate electrode and the metal strap layer in order to avoid undesirable reactions. However, the process described in this article requires a tightly controlled atmosphere and thus suffers from a small process window.